Generally, an electric equipment such as a video tape recorder having a timer function includes a micro computer for system controlling (micro computer is written as CPU, hereinafter) which controls the equipment over all and a CPU for a timer, which generates clock information and a timer controlling signal based on the clock information. These CPUs are connected each other through a communication device so as to timer-control the equipment.
FIG. 3 shows an example of the above mentioned system. Reference numeral 1 represents a CPU for system controlling and 2 represents a CPU for a timer. The CPU 1 for system controlling and the CPU 2 for a timer have communication interface circuits 14 and 21, respectively, which transfer a baseband data. These communication interface circuits 14 and 21 are connected through a line 4 so that one-to-one data transfer is available.
The CPU 1 for system controlling controls the operation of the equipment by a data generating circuit 13 connected to the communication interface circuit 14. In other words, the data generating circuit 13 generates a servo data based on a feedback signal supplied from a controlled part 3 containing a channel selecting circuit, a servo circuit or the like. Also, the data generating circuit 13 detects the condition of the controlled part 3, such as the amount of remaining tape and whether a cassette is fitted or not and generates a displaying data for displaying the condition. The above mentioned displaying data is transferred to the line 4 through the communication interface circuit 14 and received by a communication interface circuit 21 of the CPU 2 for a timer. The CPU 1 for system controlling contains a reference oscillator 12 connected with a crystal vibrator 11x and capacitance 11c, 11c' on its outside and the reference oscillator 12 generates a high frequency clock such as 10 MHz. The clock is divided into several lower frequencies by a frequency divider 15 and used as an operation clock (A) of the CPU 1. On the other hand, the clock is divided into about one hundredth by a frequency divider 16 and used as a communication clock (B). Further, the communication clock (B) is divided by a frequency divider 17 and used as a clock (C) which determines the transferring period of the above mentioned data. From the data generating circuit 13, the data is synchronized with the communication clock (B) and read out as a bit unit and transferred from the communication interface circuit 14 to the same circuit 21 as an unified data by a period T of the clock (C).
The CPU 2 for a timer is connected to a displaying circuit 5 for displaying an operating condition of the controlled part 3 and time, and an outer input circuit 6 composed of a remote control transmitter, a keyboard or the like. The CPU 2 processes an input data supplied from an outer input circuit 6 and at the same time processes a displaying data supplied from the CPU 1 for system controlling through the communication interface circuit 21 by using the data generating circuit 22. A data generating circuit 22 generates a data which sets up an operating condition of the equipment, such as a data for recording and stopping, based on the input data from the outer input circuit 6, and generates a program data which carries out a timer operation. The data for setting up an operation is transferred to the communication interface circuit 21 and sent to the CPU 1 for system controlling, and the program data is temporally stored in a memory of a timer controlling circuit 26. The program data consists of a reserved time data and an operation setting data, such as a channel data instructing selected channel. The CPU 2 for a timer contains a reference oscillator 23 which connects with a crystal vibrator 24x and capacitance 24c, 24c' on its outside and the reference oscillator 23 generates a high frequency clock in the same way as the above mentioned reference oscillator 12. The clock is divided into several lower frequencies by a frequency divider 27 and used as an operation clock (F) of the CPU 2. On the other hand, the clock is divided into about one hundredth by a frequency divider 30 and used as a time clock (G).
Also, the CPU 2 for a timer includes a clock information generating circuit 25 which counts the clock (G) obtained by dividing the output of the reference oscillator 23 contained in the CPU 2 and generates clock information. The clock information generating circuit 25 supplies generated clock information to the timer controlling circuit 26 and transfers it to the data generating circuit 22 through the timer controlling circuit 26. The timer controlling circuit 26 compares the above mentioned clock information and a reserved time data in the memory and transfers an operation setting data, such as a selecting channel data to the data generating circuit 22 when both time information coincides. The data generating circuit 22 transfers the operation setting data of the timer program to the CPU 1 for system controlling through the communication interface circuit 21. Also, the clock information transferred to the data generating circuit 22 is processed in the data generating circuit 22 and displayed on the displaying circuit 5 as a time data.
The above mentioned system controls the controlled part 3 by the CPU 1 for system controlling and regularly transfers the displaying data which shows the operating condition of the controlled part 3 to the CPU 2 for a timer so that the data can be displayed on the displaying circuit 5. Also, when the controlled part 3 is timer-controlled, an input data from the outer input circuit 6 is processed by the CPU 2 for a timer and a timer program is set in the memory of the timer controlling circuit 26. When the clock information coincides with the reserved time data in the memory, a timer operation setting data, such as a selecting channel data is transferred to the communication interface circuit 14 of the CPU 1 for system controlling through the communication interface circuit 21 and the line 4. Therefore, the data generating circuit 13 timer-controls the controlled part 3 by the data from the communication interface circuit 14.
Since the above mentioned system is composed of a digital circuit in which, for example, a servo circuit and a channel selecting circuit in the controlled part 3 process a digital signal, a highly precise clock is needed to generate a data supplied to these circuits. Thus, the CPU 1 for system controlling drives the data generating circuit 13 by the highly precise clock caused by the reference oscillator 12 fitted to the crystal vibrator 11x on its outside, and forms and processes the data corresponding to the controlled part 3 of the digital circuit structure. Also, the CPU 2 for a timer contains a highly precise reference oscillator 23 using the crystal vibrator 24x to count the clock information and carries out an accurate timer operation.
However, according to the above mentioned structure, both the CPU 1 for system controlling and the CPU 2 for a timer use crystal vibrators having a highly precise oscillating function so that the system becomes expensive.
Thus, the object of this invention is to provide a clock apparatus in which precise clock information can be generated by using only one highly precise reference oscillator.